Abstract :

In this paper the design a high- precision VLSI architecture of reconfigurable FFT processor is implemented. Basically the FFT supports the bit size which is suitable to the system and mostly used in the long term evolution systems. Transport triggered architecture is utilized to customize the size of fault free FFT processor. Here the both energy-efficiency and performance is evaluated by using the standard cell technology. Computing address unit generates the address to access the main memory. Barrel shifter is used to shift the position of bits. Data merging block will merge the bits very effectively. All the shifter data and merged data is saved in the data memory blocks. Memory access controller will control the data while accessing to the reconfigurable unit. Twiddle factor is used to speed the operation of system. At last from simulation result it can observe that reconfigurable FFT processor gives effective outcome.