Abstract :

A fault-tolerant 64x16 Random Access Memory (RAM) system has been designed and functionally verified using SystemVerilog-based verification environment. The RAM module incorporates Error Correction Code (ECC) and Built-In SelfTest (BIST) mechanisms to enhance data integrity and reliability against transient and permanent faults, which are critical in safety-critical and high-reliability systems. The ECC encoder implements a Hamming SEC-DED (Single Error Correction – Double Error Detection) scheme by generating 5 parity bits for every 16-bit data, resulting in a 21-bit encoded output. During read operations, the ECC decoder computes the syndrome to detect and correct single-bit errors and flag double-bit errors. The BIST controller automates the test process by writing known patterns into memory, reading them back, and comparing the values to detect permanent faults without external test equipment. The top-level module integrates the RAM, ECC encoder/decoder, and BIST controller. It s